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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. mos integrated circuit pd77210, 77213 16-bit fixed-point digital signal processor document no. u15203ej3v0ds00 (3rd edition) date published november 2001 ns cp(k) printed in japan data sheet ? 2001 the mark shows major revised points. the pd77210 and 77213 are 16-bit fixed-point digital signal processors (dsp). compared with the existing members of the pd77111 family, the pd77210 family consumes less power and is ideal for battery-driven mobile terminal applications such as pdas and cellular telephones. the p77210 family is dsp is also compatible with the pd77111 family at the binary level. the pd77210 family consists of the pd77210 and 77213. unless otherwise specified, the pd77210 family refers to the entire family. if there are some differences in function or operation among family products, they are described under their respective names. the functions of the pd77210 family are described in detail in the following user?s manuals. refer to these manuals when designing your system. pd77210 family user?s manual - architecture: in preparation pd77016 family user?s manual - instructions: u13116e features ? instruction cycle (operating clock): pd77210 6.25 ns min. (160 mhz max.) pd77213 8.33 ns min. (120 mhz max.) ? memory -internal instruction memory: pd77210 :ram 31.5 kwords x 32 bits pd77213 :ram 15.5 kwords x 32 bits rom 64 kwords x 32 bits -data memory: pd77210 :ram 30 kwords x 16 bits x 2 planes (x and y data memories) external memory space 1 mwords x 16 bits (common to x and y data memories) pd77213 :ram 18 kwords x 16 bits x 2 planes (x and y data memories) rom 32 kwords x 16 bits x 2 planes (x and y data memories) external memory space 1 mwords x 16 bits (common to x and y data memories) ? peripheral -audio serial interface: 1 channel -time-division serial interface: 1 channel -16-bit host interface: 1 channel -16-bit general-purpose port -16-bit timer: 2 channels -peripheral-memory dma transfer function -sd (secure digital) card interface : pd77213 only
data sheet u15203ej3v0ds 2 pd77210, 77213 ? supply voltage -dsp core supply voltage : 1.425 to 1.65 v (max. operating speed 120 mhz), 1.55 to 1.65 v (max. operating speed 160 mhz) pd77210 only -i/o pin supply voltage: 2.7 to 3.6 v ordering information parts number package pd77210f1-da2 161-pin plastic fine pitch bga (10 x 10) pd77210gj-8en 144-pin plastic lqfp (fine pitch) (20 x 20) pd77213f1-xxx-da2 161-pin plastic fine pitch bga (10 x 10) pd77213gj-xxx-8en 144-pin plastic lqfp (fine pitch) (20 x 20) remark xxx indicates rom code suffix.
data sheet u15203ej3v0ds 3 pd77210, 77213 block diagram serial i/o ( audio) peripheral unit data memory unit operation unit program control unit interrupt controller port host i/o x memory data addressing unit x memory y memory data addressing unit y memory loop control stack pc stack clock control mac 16 16 + 40 40 alu (40) r0 to r7 x bus y bus external memory reset clkout clkin cstop main bus timer ie i/o cpu control bsft serial i/o (tdm) external memory i/o peripheral-memory transfer bus peripheral bus dma controller halts stops pll instruction memory interrupt control sd card i/o note note pd77213 only
data sheet u15203ej3v0ds 4 pd77210, 77213 functional pin block mholdrq mholdak mbstb mwait ma0 to ma19 md0 to md15 mrd mwr reset intmn +1.5 v +3.3 v iv dd ev dd reset and interrupt system control clock external data memory interface serial interface (time division serial) serial interface (audio serial) host interface port for debugging 16 16 20 16 2 4 2 16 tso tsorq tsoen tsck tsi tsien tsiak clkin clkout pll0 to pll3 stops cstop halts asoen/lrclk asien/mclk asck/bclk asi aso hcs ha0, ha1 hrd hre hwr hwe hd0 to hd15 tdo, tice tck, tdi, tms, trst p0 to p15 gnd timer timout 4 sddat0 sdcr sdclk sdmon sd card interface note note pd77213 only caution some port pins, host interface pins, serial interface pins, interrupt pins, and sd card interface pins are alternate function pins. remark m, n = 0 to 3
data sheet u15203ej3v0ds 5 pd77210, 77213 pd77213 15.5 k 32 64k 32 18 k 16 each 32 k 16 each 1 m 16 (8 k 16, using sd i/f) 8.33 ns (120 mhz) sd card i/f pd77210 31.5 k 32 30 k 16 each 1 m 16 6.25 ns (160 mhz) integer multiple of 10 to 64 (external pin) 2 channels (time-division, audio) 16 bits (some are alternative with host) 2 channels (16-bit resolution) ? dsp core: 1.5 v i/o pins: 3.3 v 161-pin fbga 144-pin lqfp pd77115 11.5 k 32 none 16 k 16 each none none integer multiple of 1 to 16 (external pin) 1 channel (audio codec) 16-bit bus 8 bits 1 channel (16-bit resolution) sd card i/f 80-pin tqfp 80-pin fbga pd77114 8 k 16 each ? 100-pin tqfp pd77113a 3.5 k 32 48 k 32 16 k 16 each 32 k 16 each none ? 80-pin fbga pd77112 16 k 16 each ? 100-pin tqfp pd77111 1 k 32 31.75 k 32 3 k 16 each 16 k 16 each none 13.3 ns (75 mhz) integer multiple of 1 to 16 (mask option) ? 80-pin tqfp 80-pin fbga pd77110 35.5 k 32 none 24 k 16 each none none 32 k 16 each 15.3 ns (65 mhz) integer multiple of 1 to 8 (external pin) 2 channels (speech codec) 8-bit bus 4 bits none ? dsp core: 2.5 v i/o pins: 3 v 100-pin tqfp int. instruction ram int. instruction rom data ram (x/y memory) data rom (x/y memory) ext. instruction memory ext. data memory (x/y memory) serial interface host interface general-purpose port (i/o programmable) timer others dsp function list item memory space (words bits) instruction cycle (at maximum operating speed) multiple peripheral supply voltage package
data sheet u15203ej3v0ds 6 pd77210, 77213 pin configurations 161-pin plastic fine pitch bga (10 x 10) ? pd77210f1-da2 ? pd77213f1-xxx-da2 (bottom view) (top view) jhgfedcba abcdefghj 14 13 12 11 10 9 8 7 6 5 4 3 2 1 index mark mlk klm pn p n
data sheet u15203ej3v0ds 7 pd77210, 77213 pin no. pin name pin no. pin name pin no. pin name pin no. pin name a1 nc c14 ev dd h2 hd7 m5 tsorq a2 nc d1 p10/hd10/int22 h3 hd6 m6 ma0 a3 p5/int11 d2 p11/hd11/int32 h4 gnd m7 ma4 a4 p2/int20 d3 p12/hd12/int03 h11 md5 m8 ma5 a5 gnd d4 gnd h12 md4 m9 ma10 a6 ev dd d5 gnd h13 md1 m10 ma12 a7 iv dd d6 p1/int10 h14 md3 m11 ma15/reserved note a8 iv dd d7 gnd j1 ev dd m12 ma19/sdclk note a9 pll0 d8 gnd j2 hcs m13 ma18/sdcr note a10 stops d9 gnd j3 ha1 m14 ev dd a11 ev dd d10 gnd j4 hwr n1 nc a12 trst d11 tms j11 gnd n2 nc a13 nc d12 tice j12 md0 n3 asien/mclk a14 nc d13 md12 j13 mbstb n4 tsck b1 nc d14 md15 j14 iv dd n5 tsiak b2 nc e1 p14/hd14/int23 k1 ha0 n6 ma1 b3 p7/int31 e2 p15/hd15/int33 k2 hrd n7 ma2 b4 p6/int21 e3 p13/hd13/int13 k3 timout n8 ma7 b5 p3/int30 e4 gnd k4 aso n9 ma9 b6 clkout e5 nc k11 gnd n10 ma11 b7 iv dd e11 gnd k12 mwr n11 ma16/reserved note b8 pll3 e12 md14 k13 mwait n12 ma17/reserved note b9 pll1 e13 md9 k14 ev dd n13 nc b10 cstop e14 md11 l1 hwe n14 nc b11 i.c. f1 ev dd l2 hre p1 nc b12 tck f2 hd1 l3 gnd p2 nc b13 nc f3 hd2 l4 gnd p3 asi b14 nc f4 hd0 l5 tsien p4 tso c1 ev dd f11 md10 l6 gnd p5 tsi c2 p8/hd8/int02 f12 md13 l7 gnd p6 ev dd c3 p9/hd9/int12 f13 md7 l8 ma8 p7 iv dd c4 p4/int01 f14 ev dd l9 gnd p8 ma3 c5 p0/int00 g1 hd3 l10 ma14/sddat0 note p9 ma6 c6 clkin g2 hd5 l11 gnd p10 ev dd c7 pll2 g3 hd4 l12 mholdrq p11 ma13/sdmon note c8 halts g4 gnd l13 mrd p12 ev dd c9 reset g11 gnd l14 mholdak p13 nc c10 i.c. g12 md8 m1 ev dd p14 nc c11 tdi g13 md2 m2 asck/bclk c12 tdo g14 md6 m3 asoen/lrclk c13 gnd h1 iv dd m4 tsoen note ma13 to ma19 pins of the pd77213 are alternate function pins.
data sheet u15203ej3v0ds 8 pd77210, 77213 144-pin plastic lqfp (fine pitch) (20 x 20) (top view) ? pd77210gj-8en ? pd77213gj-xxx-8en 144 120 121 122 123 124 125 126 127 128 129 130 131 gnd 132 133 gnd 134 135 136 137 138 139 140 141 142 143 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 halts gnd clkin clkout pll0 pll2 pll1 pll3 gnd 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 hd7 hd6 hd5 hd4 hd3 hd2 hd1 hd0 gnd gnd mholdak gnd ev dd gnd mrd mwr mholdrq 26 27 28 29 30 31 32 33 34 35 36 71 70 69 68 109 110 111 112 113 114 115 116 117 118 119 gnd gnd stops cstop iv dd iv dd ev dd aso ev dd ev dd md14 md15 md13 md10 md8 md9 md12 md11 md6 md7 md4 md5 md2 md3 md0 md1 mbstb mwait reset gnd tck tdi tms i.c. i.c. ev dd trst p8/hd8/int02 p9/hd9/int12 p10/hd10/int22 p11/hd11/int32 p12/hd12/int03 p13/hd13/int13 p14/hd14/int23 p15/hd15/int33 gnd ev dd gnd ma18/sdcr note ma19/sdclk note gnd iv dd ev dd iv dd 61 60 ha1 ha0 timout 67 66 65 64 63 62 hcs hrd hre hwr hwe gnd gnd iv dd ev dd ev dd ev dd tdo tice gnd p0/int00 p2/int20 p1/int10 p3/int30 p4/int01 p5/int11 p6/int21 p7/int31 asoen/lrclk 108 107 106 105 104 103 102 101 100 99 98 97 ma9 96 ma8 95 ma7 94 93 92 91 90 89 88 87 86 85 84 ma12 ma11 ma10 gnd gnd ma13/sdmon note ma5 ma4 ma3 ma2 ma1 gnd tsiak tsorq 83 82 81 80 79 78 77 gnd 76 75 74 73 72 ev dd ma0 ma6 ev dd iv dd ma15/reserved note asien/mclk asck/bclk asi tsoen tso tsien tsi tsck ma16/reserved note ma17/reserved note ev dd ma14/sddat0 note note ma13 to ma19 pins of the pd77213 are alternate function pins.
data sheet u15203ej3v0ds 9 pd77210, 77213 pin no . pin name pin no . pin name pin no . pin name pin no . pin name 1gnd 37ev dd 73 gnd 109 gnd 2 tck 38 gnd 74 asck/bclk 110 ev dd 3 tdi 39 p8/hd8/int02 75 asien/mclk 111 ma18/sdcr note 4 tms 40 p9/hd9/int12 76 asi 112 ma19/sdclk note 5 trst 41 p10/hd10/int22 77 tsoen 113 mholdrq 6 i.c. 42 p11/hd11/int32 78 tso 114 mholdak 7 i.c. 43 p12/hd12/int03 79 tsck 115 mrd 8ev dd 44 p13/hd13/int13 80 tsien 116 mwr 9 gnd 45 p14/hd14/int23 81 tsi 117 mwait 10 reset 46 p15/hd15/int33 82 tsorq 118 mbstb 11 stops 47 ev dd 83 tsiak 119 md0 12 cstop 48 gnd 84 ma0 120 md1 13 halts 49 hd0 85 ma1 121 ev dd 14 pll0 50 hd1 86 ev dd 122 gnd 15 pll1 51 hd2 87 gnd 123 iv dd 16 pll2 52 hd3 88 iv dd 124 gnd 17 pll3 53 hd4 89 gnd 125 md2 18 iv dd 54 hd5 90 ma2 126 md3 19 gnd 55 hd6 91 ma3 127 md4 20 clkin 56 hd7 92 ma4 128 md5 21 iv dd 57 iv dd 93 ma5 129 md6 22 gnd 58 gnd 94 ma6 130 md7 23 iv dd 59 ev dd 95 ma7 131 md8 24 gnd 60 gnd 96 ma8 132 md9 25 clkout 61 hcs 97 ma9 133 ev dd 26 ev dd 62 ha0 98 ev dd 134 gnd 27 gnd 63 ha1 99 gnd 135 md10 28 p0/int00 64 hrd 100 ma10 136 md11 29 p1/int10 65 hre 101 ma11 137 md12 30 p2/int20 66 hwr 102 ma12 138 md13 31 p3/int30 67 hwe 103 ma13/sdmon note 139 md14 32 p4/int01 68 timout 104 ma14/sddat0 note 140 md15 33 p5/int11 69 asoen/lrclk 105 ma15/reserved note 141 tdo 34 p6/int21 70 aso 106 ma16/reserved note 142 tice 35 p7/int31 71 ev dd 107 ma17/reserved note 143 gnd 36 gnd 72 gnd 108 ev dd 144 ev dd note ma13 to ma19 pins of the pd77213 are alternate function pins.
data sheet u15203ej3v0ds 10 pd77210, 77213 pin name asck :audio serial clock input/output asi :audio serial data input asien :audio serial input enable aso :audio serial data output asoen :audio serial output enable bclk :bit clock input/output clkin :clock input clkout :clock output cstop :clear stop mode ev dd :power supply for i/o pins gnd :ground halts :halt status signal output hd0 to hd15 :host data bus hcs :host chip select ha0, ha1 :host data access hrd :host read hre :host read enable hwe :host write enable hwr :host write i.c. :internal connection iv dd :power supply for dsp core intmn :interrupt (m,n=0 to 3) lrclk :left right clock input/output ma0 to ma19 :external data memory address bus mbstb :external data memory bus strobe mclk :master clock input md0 to md15 :external data memory bus mholdak :external data memory bus hold acknowledge mholdrq :external data memory bus hold request mrd :external data memory read output mwr :external data memory write output mwait :external data memory access wait input nc :non-connection p0 to p15 :port pll0-pll3 :pll multiple rate set reserved :reserved reset :reset sdclk :sd card clock output sdcr :sd card command output/response input sddat0 :sd card data input/output sdmon :sd card access monitor stops :stop status signal output tck :test clock input tdi :test data input tdo :test data output tice :test in-circuit emulator timout :timer time out monitor output tms :test mode select trst :test reset tsck :time division multiplex serial clock input tsi :time division multiplex serial data input tsiak :time division multiplex serial input acknowledge tsien :time division multiplex serial input enable tso :time division multiplex serial data output tsoen :time division multiplex serial output enable tsorq :time division multiplex serial output request
data sheet u15203ej3v0ds 11 pd77210, 77213 contents 1. pin functions............................................................................................................. .......................13 1.1 description of pin functions .............................................................................................. ..........................13 1.2 connection of unused pins ................................................................................................. .........................21 1.2.1 connection of functional pins ........................................................................................... .......................21 1.2.2 connection of non-functional pin ........................................................................................ .....................22 2. functional outline ........................................................................................................ ...............23 2.1 program control unit...................................................................................................... ...............................23 2.1.1 cpu control ............................................................................................................. ................................23 2.1.2 interrupt control ....................................................................................................... ................................23 2.1.3 loop control stack ...................................................................................................... .............................23 2.1.4 pc stack ................................................................................................................ ..................................23 2.1.5 clock control........................................................................................................... .................................23 2.1.6 instruction memory ...................................................................................................... ............................24 2.2 operation unit ............................................................................................................ ....................................24 2.2.1 general-purpose registers (r0 to r7) .................................................................................... .................24 2.2.2 multiply accumulator (mac) .............................................................................................. ......................24 2.2.3 arithmetic logic unit (alu) ............................................................................................. ..........................24 2.2.4 barrel shifter (bsft)................................................................................................... .............................24 2.3 data memory unit.......................................................................................................... .................................24 2.3.1 data memory ............................................................................................................. ..............................24 2.3.2 data addressing unit.................................................................................................... ............................25 2.4 peripheral unit........................................................................................................... .....................................25 2.4.1 serial interface (sio) .................................................................................................. .............................25 2.4.2 host interface (hio).................................................................................................... .............................25 2.4.3 general-purpose i/o port (pio) .......................................................................................... .....................26 2.4.4 external memory interface (mio)......................................................................................... ....................26 2.4.5 timers (tim1 and tim2) .................................................................................................. ........................26 2.4.6 interrupt controller (intc)............................................................................................. ...........................26 2.4.7 dma controller (pmt) .................................................................................................... ..........................26 2.4.8 sd card interface (sdcif)............................................................................................... ........................26 2.4.9 debug interface (ieio).................................................................................................. ...........................26 3. clock generator........................................................................................................... ................27 4. reset function ............................................................................................................ ....................28 4.1 hardware reset ............................................................................................................ ..................................28 5. function of boot-up rom.................................................................................................. .........28 5.1 boot at reset ............................................................................................................. .....................................28 5.1.1 memory boot............................................................................................................. ...............................28 5.1.2 host boot ............................................................................................................... ..................................29 5.1.3 serial boot ............................................................................................................. ..................................29 5.2 reboot.................................................................................................................... .........................................29 5.2.1 memory reboot ........................................................................................................... .............................29
data sheet u15203ej3v0ds 12 pd77210, 77213 5.2.2 host reboot ............................................................................................................. ................................ 30 5.2.3 serial reboot ........................................................................................................... ................................ 30 6. standby mode.............................................................................................................. .................... 31 6.1 halt mode ................................................................................................................. ...................................... 31 6.2 stop mode ................................................................................................................. ..................................... 31 7. memory map................................................................................................................ ...................... 32 7.1 instruction memory ........................................................................................................ ............................... 32 7.1.1 instruction memory map .................................................................................................. ....................... 32 7.1.2 interrupt vector table.................................................................................................. ............................. 33 7.2 data memory ............................................................................................................... ................................... 34 7.2.1 data memory map ......................................................................................................... ......................... 34 7.2.2 internal peripherals .................................................................................................... ............................. 35 8. general-purpose port and interrupt ............................................................................... 38 8.1 general-purpose port pins ................................................................................................. .......................... 38 8.2 interrupt pin ............................................................................................................. ...................................... 38 9. instruction ................................................................................................................ ....................... 39 9.1 outline of instruction .................................................................................................... ................................ 39 9.2 instruction set and its operation......................................................................................... ........................ 40 10. electrical specifications................................................................................................ ....... 46 11. package drawings......................................................................................................... ............. 69 12. recommended soldering conditions................................................................................. 71
data sheet u15203ej3v0ds 13 pd77210, 77213 1. pin functions because the pin numbers differ depending on the package, see the column for the package to be used in the tables below. 1.1 description of pin functions ? ? ? ? power supply pins pin no. pin name 144-pin lqfp 161-pin fbga i/o function alternate pin iv dd 18,21,23,57, 88,123 a7,a8,b7,h1, j14, p7 ? power supply for dsp core (+1.5 v) these pins supply power to the dsp core. ? ev dd 8,26,37,47,59, 71,86,98,108, 110,121,133, 144 a6,a11,c1, c14,f1,f14, j1,k14,m1, m14,p6,p10, p12 ? power supply for i/o (+3.3 v) these pins supply power to the external interface pins. ? gnd 1,9,19,22,24, 27,36,38,48, 58,60,72,73, 87,89,99,109, 122,124,134, 143 a5,c13,d4,d5, d7,d8,d9,d10, e4,e11,g4, g11,h4,j11, k11,l3,l4,l6, l7,l9,l11 ? ground these are ground pins. ? remark please supply voltage to the iv dd and ev dd pins simultaneously.
data sheet u15203ej3v0ds 14 pd77210, 77213 ? ? ? ? clock and system control pins pin no. pin name 144-pin lqfp 161-pin fbga i/o function alternate pin clkin 20 c6 input clock input this pin inputs a clock to operate the pd77210 family. ? clkout 25 b6 output internal system clock output this pin outputs the internal system clock that is the clock input from clkin and which is multiplied by the pll circuit. ? pll0 to pll3 14 to 17 a9,b9,c7,b8 input pll multiple setting input these pins set a clock multiple of the pll circuit. pll3: pll2: pll1: pll0 0000: x10 0001: x12 0010: x14 0011: x16 0100: x18 0101: x20 0110: x22 0111: x24 1000: x26 1001: x28 1010: x30 1011: x32 1100: x40 1101: x48 1110: x56 1111: x64 ? halts 13 c8 output halt mode status output this pin is asserted active in halt mode and stop mode. ? stops 11 a10 output stop mode status output this pin is asserted active in stop mode. ? cstop 12 b10 input stop mode clear signal input stop mode is cleared when this pin is asserted active. ?
data sheet u15203ej3v0ds 15 pd77210, 77213 ? ? ? ? reset and interrupt pins pin no. pin name 144-pin lqfp 161-pin fbga i/o function alternate pin reset 10 c9 input internal system reset si gnal input this pin initializes the pd77210 family. ? int00 28 c5 input p0 int01 32 c4 input p4 int02 39 c2 input p8/hd8 int03 43 d3 input p12/hd12 int10 29 d6 input p1 int11 33 a3 input p5 int12 40 c3 input p9/hd9 int13 44 e3 input p13/hd13 int20 30 a4 input p2 int21 34 b4 input p6 int22 41 d1 input p10/hd10 int23 45 e1 input p14/hd14 int30 31 b5 input p3 int31 35 b3 input p7 int32 42 d2 input p11/hd11 int33 46 e2 input maskable external interrupt input these pins input external interrupts. p15/hd15
data sheet u15203ej3v0ds 16 pd77210, 77213 ? ? ? ? external data memory interface pin no. pin name 144-pin lqfp 161-pin fbga i/o function alternate pin ma0 to ma19 note 84, 85, 90 to 97, 100 to 107, 111, 112 m6,n6,n7,p8, m7,m8,p9,n8, l8,n9,m9,n10, m10,p11,l10, m11,n11,n12, m13,m12 output (3s) address bus of external data memory these pins output an address when the external data memory is accessed. sdclk, sdcr, sddat0, sdmon md0 to md15 119,120, 125 to 132, 135 to 140 j12,h13,g13, h14,h12,h11, g14,f13,g12, e13,f11,e14, d13,f12,e12, d14 i/o (3s) 16-bit data bus these pins input/output data when the external data memory is accessed. ? mwr 116 k12 output (3s) write output this pin outputs a write strobe signal for the external data memory. ? mrd 115 l13 output (3s) read output this pin outputs a read strobe signal for the external data memory. ? mholdak 114 l14 output hold acknowledge signal this pin goes low when the external device is granted use of the external data memory bus of the pd77210 family. ? mholdrq 113 l12 input hold request signal the external device inputs a low level to this pin when it uses the external data memory bus of the pd77210 family. ? mwait 117 k13 input wait signal input this pin inserts wait cycles w hen the pd77210 family accesses the external data memory. ? 0: inserts wait cycles. ? 1: does not insert wait cycles. ? mbstb 118 j13 output bus strobe signal this pin goes low while the pd77210 family uses the external data memory bus. ? note ma13 to ma19 pins of the pd77213 are alternate function pins. remark those pins marked ?3s? in the above table enter the high-impedance state under the following conditions: ma0 to ma19, mrd, and mwr: when the bus is released (mholdak = low level) md0 to md15: when the external data memory is not accessed and when the bus is released (mholdak = low level)
data sheet u15203ej3v0ds 17 pd77210, 77213 ? ? ? ? timer pin no. pin name 144-pin lqfp 161-pin fbga i/o function alternate pin timout 68 k3 output time out monitor this pin is asserted active when the timer times out. ? ? ? ? ? serial interface pin no. pin name 144-pin lqfp 161-pin fbga i/o function alternate pin asck/ bclk 74 m2 i/o audio serial clock input/output asck:audio serial clock input bclk:serial clock i/o ? aso 70 k4 output (3s) audio serial data output ? asi 76 p3 input audio serial data input ? asoen/ lrclk 69 m3 i/o audio serial output enable/left right clock input output asoen:audio serial output enable input lrclk:left right clock i/o ? asien/ mclk 75 n3 input audio serial input enable/master clock input output asien:audio serial input enable input mclk:master clock input (in master mode) ? tsck 79 n4 input clock input for time division serial ? tso 78 p4 output (3s) time-division serial data output ? tsi 81 p5 input time-division serial data input ? tsorq 82 m5 output time-division serial output request ? tsoen 77 m4 input time-division serial output enable ? tsien 80 l5 input time-division serial input enable ? tsiak 83 n5 output time-division serial input acknowledge ? remark those pins marked ?3s? in the above table enter the high-impedance state when data transmission is completed and when the hardware reset (reset) signal is input.
data sheet u15203ej3v0ds 18 pd77210, 77213 ? ? ? ? host interface pin no. pin name 144-pin lqfp 161-pin fbga i/o function alternate pin ha1 63 j3 input host address 1 this pin specifies a register that is accessed by the host interface pins (hd7 to hd0, or hd15 to hd0). ? 1: the host interface status register (hst) is accessed. ? 0: the host transmit data register (hdt (out)) is accessed for read (hrd = 0) and the host receive data register (hdt (in)) is accessed for write (hwr = 0). ? ha0 62 k1 input host address 0 this pin specifies a register that is accessed by hd7 to hd0 in 8-bit mode. this pin is invalid in 16-bit mode. ? 1: bits 15 to 8 of hst, hdt (in), and hdt (out) are accessed. ? 0: bits 7 to 0 of hst, hdt (in), and hdt (out) are accessed. ? hcs 61 j2 input chip select input ? hrd 64 k2 input host read input ? hwr 66 j4 input host write input ? hre 65 l2 output host read enable output ? hwe 67 l1 output host write enable output ? hd0 to hd7 49 to 56 f4,f2,f3,g1, g3,g2,h3,h2 i/o (3s) 8-bit host data bus these pins constitute a host data bus in 8-bit host mode. access to 16-bit data for input/output is controlled by the ha0 pin, and the data is accessed two times such that it is divided into two blo cks of 8- bit data. in 16-bit mode, the lower 8 bits of the data are input/output. ? hd8 to hd15 39 to 46 c2,c3,d1,d2, d3,e3,e1,e2 i/o (3s) host data bus these pins constitute a host data bus in 16-bit host mode. they input/output 16-bit data with hd0 to hd7. p8 to p15/ int02, int12, int22, int32, int03, int13, int23, int33 remark those pins marked ?3s? in the above table enter the high-impedance state while the host interface is not being accessed.
data sheet u15203ej3v0ds 19 pd77210, 77213 ? ? ? ? i/o port pin no. pin name 144-pin lqfp 161-pin fbga i/o function alternate pin p0 28 c5 i/o int00 p1 29 d6 i/o int10 p2 30 a4 i/o int20 p3 31 b5 i/o int30 p4 32 c4 i/o int01 p5 33 a3 i/o int11 p6 34 b4 i/o int21 p7 35 b3 i/o int31 p8 39 c2 i/o int02/hd8 p9 40 c3 i/o int12/hd9 p10 41 d1 i/o int22/hd10 p11 42 d2 i/o int32/hd11 p12 43 d3 i/o int03/hd12 p13 44 e3 i/o int13/hd13 p14 45 e1 i/o int23/hd14 p15 46 e2 i/o general-purpose i/o port int33/hd15 ? ? ? ? debugging interface pin no. pin name 144-pin lqfp 161-pin fbga i/o function alternate pin tdo 141 c12 output (3s) ? tice 142 d12 output ? tck 2 b12 input ? tdi 3 c11 input ? tms 4 d11 input ? trst 5 a12 input for debugging this interface pins are used when a debugger is used. ? remark those pins marked ?3s? in the above table enter the high-impedance state while the debugging interface is not being accessed.
data sheet u15203ej3v0ds 20 pd77210, 77213 ? ? ? ? sd card interface ( pd77213 only) pin no. pin name 144-pin lqfp 161-pin fbga i/o function alternate pin sdclk 112 m12 output sd card clock output ? leave this pin open. ma19 sdcr 111 m13 i/o (3s) sd cord command/response input : response output : command ? leave pull-up. ma18 sddat0 104 l10 i/o (3s) sd card data input/output input : read data output : write data ? leave pull-up. ma14 sdmon 103 p11 output sd card interface access monitor this pin outputs a high level when the sd card interface is being accessed. 1: sd card interface being accessed 0: sd card interface not being accessed ma13 reserved 105 to 107 m11, n11, n12 ? reserved for future function expansion. this pin becomes high impedance when the sd card interface is being used. ma15 to ma17 remark those pins marked ?3s? in the above table enter the high-impedance state when the sd card interface is not being accessed. ? ? ? ? others pin no. pin name 144-pin lqfp 161-pin fbga i/o function alternate pin i.c. 6, 7 b11, c10 ? internally connected. leave these pins open. ? nc ? a1,a2,a13, a14,b1,b2, b13,b14,e5, n1,n2,n13, n14,p1,p2, p13,p14 ? no connection. leave these pins open. ? caution if any signal is input to these pins or if these pins are read, the correct operation of the pd77210 family is not guaranteed.
data sheet u15203ej3v0ds 21 pd77210, 77213 1.2 connection of unused pins 1.2.1 connection of functional pins connect the unused pins as shown in the table below. pin name i/o recommended connection stops, halts output leave open. cstop input connect to gnd via a pull-down resistor. clkout output leave open. p0 to p15 i/o connect to ev dd via a pull-up resistor or to gnd via a pull-down resistor. hd0 to hd7 note 1 i/o connect to ev dd via a pull-up resistor or to gnd via a pull-down resistor. ha0, ha1 input connect to ev dd via a pull-up resistor or to gnd via a pull-down resistor. hcs, hrd, hwr input connect to ev dd via a pull-up resistor. hre, hwe output leave open. timout output leave open. asck, tsck input asi, tsi input connect to ev dd via a pull-up resistor or to gnd via a pull-down resistor. asien, tsien input asoen, tsoen, lrclk input connect to gnd via a pull-down resistor. aso, tso output tsorq output tsiak output leave open. ma0 to ma19 output leave open. md0 to md15 note 2 i/o connect to ev dd via a pull-up resistor or to gnd via a pull-down resistor. mrd, mwr output leave open. mholdrq input connect to ev dd via a pull-up resistor. mbstb, mholdak output leave open. mwait input connect to ev dd via a pull-up resistor. tck input connect to gnd via a pull-down resistor. tdo, tice output leave open. tms, tdi input leave open (this pin is internally pulled up). trst input leave open (this pin is internally pulled down). notes 1. these pins may left opened if the hcs, hrd,and hwr are fixed to the high level. however, connect these pins as recommended in the halt and stop modes when the power consumption must be lowered. 2. these pins may leave opened if the external data memory is not accessed in the program. however, connect these pins as recommended in the halt and stop modes when the power consumption must be lowered. caution unused alternate-function pins should be handled in accordance with the processing specified for the pin function of the initial setting.
data sheet u15203ej3v0ds 22 pd77210, 77213 1.2.2 connection of non-functional pin pin name i/o recommended connection i.c. ? leave open. nc ? leave open.
data sheet u15203ej3v0ds 23 pd77210, 77213 2. functional outline 2.1 program control unit this unit controls the execution of pd77210 family by executing instructions and controlling branching, loop, interrupts, clock, and standby mode. 2.1.1 cpu control a three-stage pipeline architecture is employed so that all instructions, except branch instructions and some others, can be executed with one system clock. 2.1.2 interrupt control the interrupt control circuit services the interrupt requests input to the interrupt controller by an external pin (intmn) or internal peripherals (such as the serial interface, host interface, timer, and dma controller). the interrupt of each interrupt source can be individually enabled or disabled. in addition, multiple interrupts are also supported. 2.1.3 loop control stack a loop function without any hardware overhead is realized. a 4-level loop stack is provided to support multiple loops. 2.1.4 pc stack a 15-level pc stack that stacks the program counter supports multiple interrupts/subroutine calls. 2.1.5 clock control a pll and a divider are internally provided as a clock generator so that an externally input clock is multiplied or divided and supplied as the operating clock to the pd77210 family. the multiple of the pll can be set by using external pins (pll0 to pll3) within a range of 10 to 64. the division ratio can be set by using a register in a range of 1 to 16. the clock control register (clkc) controls the power (on/off) to the pll, selects a clock source, controls the output divider, and controls the output of the clkout pin. two types of standby modes are available so that the power consumption can be reduced when the pd77210 family is standing by. ? halt mode: current consumption falls to several ma upon execution of the halt instruction. this mode is released by an interrupt or hardware reset. ? stop mode: current consumption falls to hundreds of a note upon execution of the stop instruction. this mode is released by hardware reset or inputting a signal to cstop pin. note when the pll is stopped
data sheet u15203ej3v0ds 24 pd77210, 77213 2.1.6 instruction memory of the instruction ram, 64 words are allocated as interrupt vectors. the pd77210 is provided with an instruction ram of 31.5 kwords. the pd77213 is provided with an instruction ram of 15.5 kwords and instruction rom of 64 kwords. a boot-up rom that boots up the instruction ram is also provided, and the instruction ram can be initialized or rewritten by means of a memory boot (booting from an internal or external data space), host boot (booting via a host interface), or serial boot (booting via a serial interface). 2.2 operation unit this unit performs multiplication, addition, logic, and shift operations, and consists of a 40-bit multiply accumulator, a 40-bit data alu, a 40-bit barrel shifter, and eight 40-bit general-purpose registers. 2.2.1 general-purpose registers (r0 to r7) these eight 40-bit registers input/output operands and load/store data to/from data memory. each register consists of three parts: r0l to r7l (bits 15 to 0), r0h to r7h (bits 31 to 16), and r0e to r7e (bits 39 to 32). depending on the type of the operation, rnl, rnh, and rne are used either as one register or in combination. 2.2.2 multiply accumulator (mac) the multiply accumulator performs multiplication of two 16-bit data items and addition or subtraction between the result of the multiplication and one 40-bit data item, and then outputs 40-bit data. a shifter (msft: mac shifter) is provided at the preceding stage of the mac, so that the 40-bit data that is to be added to or subtracted from the multiplication result can be arithmetically shifted 1 bit or 16 bits to the right before addition or subtraction. 2.2.3 arithmetic logic unit (alu) the alu accepts one or two 40-bit data items as input, performs an arithmetic or logical operation, and then outputs 40-bit data. 2.2.4 barrel shifter (bsft) the bfst accepts 40-bit data items as input, shifts the data to the left or right by an arbitrary number of bits, and then outputs 40-bit data. the data can be shifted to the right arithmetically, in which case the sign of the data is extended, or logically in which case 0 is inserted starting from the msb. 2.3 data memory unit the data memory unit consists of two planes of data memory spaces and two pairs of data addressing units. 2.3.1 data memory two data memory planes (x data memory and y data memory) are provided. the data memory space includes a 64-word peripheral area. the pd77210 has a data ram consisting of 30 kwords 2 planes. the pd77213 has a data ram consisting of 18 kwords 2 planes, and has a data rom consisting of 32 kwords 2 planes. in addition, they also have an external data memory interface that is used to connect an external 1 mword data memory to the device.
data sheet u15203ej3v0ds 25 pd77210, 77213 2.3.2 data addressing unit an independent data addressing unit is provided for each of the x and y data memory spaces. each data addressing unit has four data pointers (dpn), four index registers (dnn), one module register (dmx or dmy), and an address alu. 2.4 peripheral unit the peripheral unit has serial interfaces, a host interface, general-purpose i/o ports, timers, an external memory interface, and sd card interface ( pd77213 only). all these internal peripherals are mapped to the x and y data memory spaces and are accessed as memory-mapped i/os by the program. 2.4.1 serial interface (sio) two serial interface channels, an audio serial interface (asio) and a time-division serial interface (tdmsio), are provided. the audio serial interface can be used in either of two modes: audio mode and standard mode. the standard mode is compatible with the existing pd77111 family. the audio mode is compatible with the pd77115. the features of the audio mode are as follows: ? mode: master mode and slave mode master mode: supports master clock input (mclk), bit clock output (bclk), lr clock output (lrclk), 256 fs, 384 fs, and 512 fs. slave mode: bit clock input (bclk) and lr clock input (lrclk) ? frame format: 32- or 64-bit audio formats (lrclk format) ? handshake: handshaking with external devices by a dedicated frame signal (lrclk) and with the internal circuitry by polling, wait, or interrupt the standard mode has the following features: ? serial clock: supplied from an external source to each channel. the clock is shared for input and output by each channel. ? frame length: 8 or 16 bits, with msb or lsb first selected for each channel. ? handshake: handshaking with the external device by using a dedicated status signal and with the internal circuitry by polling, wait, or interrupt. the time-division serial interface divides the serial input/output signal into 1 to 32 time slots and allows several devices to share the serial bus. because the t1 and e1 frame signals are considered. the time slot can be extended from 1 to 128. 2.4.2 host interface (hio) this is a parallel port that inputs/outputs data from/to an external host cpu and dma controller. it can be used in either 8-bit parallel mode or 16-bit parallel mode. in the pd77210 family, 16-bit registers are mapped to memory for input data, output data, and status. handshaking with an external device is performed by using a dedicated status signal, and the internal circuitry handshaking is done by means of polling, wait, or interrupts. the 8-bit parallel mode is compatible with the existing members of the pd77111 family. in 16-bit parallel mode, some port pins are used as host interface pins.
data sheet u15203ej3v0ds 26 pd77210, 77213 2.4.3 general-purpose i/o port (pio) this is a 16-bit i/o port that can be set to either input or output mode in 1-bit units. the external pins alternate between interrupt pins and host interface pins. by setting the mode of 8 bits of the port to host interface pin mode, the host interface can be set in the 16-bit parallel mode. 2.4.4 external memory interface (mio) this interface accesses an external 1 mwords data memory area in either of two modes: direct access and dma access modes. in dma access mode, access is made via a memory-mapped register. in direct access mode, the data paging register (dpr) is set to 0x3f and a page area is accessed as an access window. an address of the external memory consists of 20 bits with the 8-bit value of the index register added as bits 12 to 19. in dma access mode, the address is automatically updated when a memory-mapped register is accessed. the address is updated in an increment addressing mode in which the address is simply incremented, or in two- dimensional addressing mode in which an offset is added to each line length. the number of wait cycles to be inserted when the external memory is accessed can be specified by a register (mwait), within a range of 1 to 15. in addition, wait cycles can also be inserted by using the mwait pin. 2.4.5 timers (tim1 and tim2) the pd77210 family has two timer channels. these timers can be used as interval timers, event counters, watchdog timers, and free-run timers. the clock input to the timers is selected from the system clock, serial clock (asck or tsck), external interrupt (int00, int10, int20, or int30), or output of each timer. the count value is 16 bits and the clock input by the prescaler can be divided by 1, 2, 4, 8, 16, 32, 64, or 128. 2.4.6 interrupt controller (intc) the interrupt controller has functions for selecting and masking interrupt signals. it controls the interrupt signal to be input to the dsp core. 2.4.7 dma controller (pmt) the dma controller realizes data transfer between the peripherals and memory (peripheral-memory transfer) in the background. it mitigates the software overhead generated by interrupt processing of the data input/output via sio, hio, mio, and sdcif ( pd77213 only). data of 14 kwords at addresses 0x0000 to 0x37ff of the internal data ram can be transferred by means of dma. 2.4.8 sd card interface (sdcif) the pd77213 supports sd card interface. this interface is for access of sd card. it supports the dma transfer for input data to internal data ram. the sd card is accessed by using a dedicated routine of system rom. 2.4.9 debug interface (ieio) the pd77210 family has the following functions that conform to the jtag (joint test action group) interface as a debug interface. a device conforming to jtag has an access port dedicated to testing and can be tested independently of the internal logic. the pd77210 family has registers and a control circuit for in-circuit emulation, in addition to the instruction registers, bypass registers, and boundary scan registers that are required by the jtag recommendation.
data sheet u15203ej3v0ds 27 pd77210, 77213 3. clock generator the clock generator generates an internal system clock based on the external clock input from the clkin pin and supplies the clock to the pd77210 family. the configuration of the clock generator is as illustrated below. stop pll controller output divider halt internal system clock x m (m:10 to 64) clkout clkin n (n:1 to 16) pll0 to pll3 clkc register peripheral bus standby mode the pll is stopped immediately after reset. the clock input from the clkin pin is directly supplied to the pd77210 family internal circuitry and bootup commences. the pll is started up in the boot routine and booting is carried out via the pll output clock (except in the case of non-boot or external memory boot). in the case of non- boot or external memory boot, when booting has finished, after the pll is started up by setting the clkc register from the user program, the clock source must be switched to the pll, in which case the pll must be locked. note that 300 s are required between when the pll is started up and when it is locked. the pll multiplication rate is specified by the external pins pll0 to pll3. the pll also has two lock range modes: 80 to 120 mhz and 120 to 160 mhz. the mode to be used is specified by the p3 pin during booting. the clkc register is used to control turning on/off the pll, select the clock source (external clock/multiplied clock/divided or non-divided output), control resetting the output divider, set the division ratio, and enable/disable clkout pin output. when the output divider is selected, the high-level width of the clock output by the clkout pin is equivalent to 1 cycle of the normal operation (which means that the clock does not have a duty factor of 50%). in halt mode, output of the divider circuit is automatically selected as the clock source. when the divider circuit is selected, the clock is not changed even if halt mode is set. in stop mode, the system clock supplied to the internal circuitry is masked. because the pll is not stopped automatically, it can recover from stop mode without pll lock time. it is necessary to set the clkc register by the program to stop the pll.
data sheet u15203ej3v0ds 28 pd77210, 77213 4. reset function the device is initialized when a low level of the specified width is input to the reset pin. 4.1 hardware reset the internal circuitry of the pd77210 family is initialized when the reset pin is asserted active (low level) for a specific period. when the reset pin is then deasserted inactive (high level), booting of the instruction ram is performed in accordance with the status of the port pins (p0, p1, p2, and p3), and then processing is executed starting from the instruction at address 0x200 (reset entry) of the instruction memory. 5. function of boot-up rom the instruction ram is booted up by using the internal boot-up rom when power is applied or when the contents of the instruction memory are to be rewritten by the program. 5.1 boot at reset immediately after release of a hardware reset, the boot program first reads general-purpose i/o port pins p0 to p3, and a boot mode (memory boot/host boot/serial boot) is determined by the bit patterns of these port pins. once the booting processing has been completed, processing is executed starting from the instruction at address 0x200 (reset entry) of the instruction memory. p2 p1 p0 boot mode 0 0 0 non-boot note 0 0 1 x memory initial boot 0 1 0 y memory initial boot 0 1 1 xy memory initial boot 1 0 0 external memory initial boot 1 0 1 host boot 1 1 0 serial boot note this setting is used when the pd77210 family must be reset upon restoration from standby mode after a reset boot has been executed once. p3 pll lock range 0 120 to 160 mhz 1 80 to 120 mhz 5.1.1 memory boot the instruction code stored in data memory is transferred to the instruction ram. depending on the data memory from which the instruction code is to be transferred, x memory boot (booting from the x data memory), y memory boot (booting from the y data memory), xy memory boot (booting from the x and y data memories), or external memory boot (booting from the external data memory space) may be performed.
data sheet u15203ej3v0ds 29 pd77210, 77213 5.1.2 host boot the boot parameter and instruction code are obtained via the host interface and transferred to the instruction ram. 5.1.3 serial boot the boot parameter and instruction code are obtained via the serial interface and transferred to the instruction ram. 5.2 reboot the contents of the instruction ram can be rewritten by calling the following reboot entries by the program. parameter reboot mode entry address number of instruction steps transfer source start address transfer destination transfer destination start address transfer destination page (dpr) x memory 0x1 r7l dp3 r6l dp2 r5l y memory 0x2 r7l dp7 r6l dp6 r5l xy memories 0x3 r7l dp3, dp7 r6l dp2 r5l memory reboot external memory 0x4 r7l dp3 r6l dp2 r5l host reboot 0x5 r7l ? r6l dp2 r5l serial reboot 0x6 r7l ? r6l dp2 r5l 5.2.1 memory reboot the instruction code stored into data memory is transferred to the instruction ram. depending on the data memory from which the instruction code is to be transferred, x memory reboot (rebooting from the x data memory), y memory reboot (rebooting from the y data memory), xy memory reboot (rebooting from the x and y data memories), or external memory reboot (rebooting from the external data memory space) may be performed. perform memory rebooting by setting the following parameters and calling the entry address by the corresponding rebooting method. ? r7l: number of instruction steps to be rebooted ? dp3: first address of x memory storing instruction code (to reboot from x, xy or external memories) ? dp7: first address of x memory storing instruction code (to reboot from y or xy memories) ? r6l: transfer source data page register (dpr) (specify 0x00 in the case of the internal data ram area.) index register (for external memory rebooting) ? dp2: transfer destination address of the instruction to be rebooted (to reboot from x, xy or external memories) ? dp6: transfer destination address of the instruction to be rebooted (to reboot from y memories) ? r5l: transfer destination page register (dpr) (specify 0x80 in the case of the internal instruction ram area.)
data sheet u15203ej3v0ds 30 pd77210, 77213 5.2.2 host reboot the instruction code is obtained via the host interface and transferred to the instruction ram. the entry address is 0x5. host rebooting is executed by setting the following parameters and then calling this address. ? r7l: number of instruction steps to be rebooted ? r6l: host status register (hst) ? dp2: transfer destination address of instruction to be rebooted (offset 0x8000 in the case of internal instruction ram area) ? r5l: transfer destination data page register (dpr) (specify 0x80 of the internal instruction ram area.) 5.2.3 serial reboot the instruction code is obtained via the serial interface (tdmsio) and then transferred to the instruction ram. the entry address is 0x6. host rebooting is executed by setting the following parameters and then calling this address. ? r7l: number of instruction steps to be rebooted ? r6l: serial status register (sst) (specify 0x0ec0.) ? dp2: transfer destination address of instruction to be rebooted (offset 0x8000 in the case of internal instruction ram area) ? r5l: transfer destination data page register (dpr) (specify 0x80 of the internal instruction ram area.)
data sheet u15203ej3v0ds 31 pd77210, 77213 6. standby mode the pd77210 family can be set to either of two standby modes. each mode can be set by executing the corresponding instruction. the power consumption can be reduced in these modes. 6.1 halt mode the halt mode can be set by executing the halt instruction. in this mode, all the functions except the clock circuit and pll are stopped and, therefore, the current consumption can be reduced. the device can be released from this mode by an interrupt or hardware reset. to release the device from halt mode by issuing an interrupt, the contents of the internal registers and memories are retained. it takes 10 to 20 system clocks to release the pd77210 family from halt mode (if it is released by an interrupt). when releasing the device from halt mode by using hardware reset, the external clock must be selected as the clock source in advance that the contents of memories are retain. in halt mode, the clock circuit of the pd77210 family supplies the clock divided by the ratio specified by the clkc register as the internal system clock. the same applies to the clock output by the clkout pin. 6.2 stop mode stop mode is set when a stop instruction is executed. in this mode, supply of the clock to the internal system is stopped. if the pll is stopped before stop mode is set, all the functions, including the clock circuit and pll, are stopped. as a result, only a leakage current flows and, therefore, the current consumption can be minimized. in this case, the external clock must be selected as the clock source in advance. the device is released from stop mode by a hardware reset or the cstop pin. to release the device from stop mode by using the cstop pin, the contents of the internal registers and memories are retained. when releasing the device from stop mode by using hardware reset, the external clock must be selected as the clock source in advance that the contents of memories are retain.
data sheet u15203ej3v0ds 32 pd77210, 77213 7. memory map the pd77210 family employs a harvard architecture that separates the instruction memory space from the data memory space. 7.1 instruction memory 7.1.1 instruction memory map the instruction memory space consists of 64 kwords 32 bits. the area at addresses 0x8000 to 0xffff is a paging area that supports a memory space of 64 kwords or more by specifying a page by using the instruction paging register (ipr). the instruction rom of the pd77213 exists in the paging area and is accessed as ipr=0x0 or 0x1. the paging area of the pd77210 is reserved for future expansion. instruction ram (15.5 kwords) 0xffff 0x8000 0x7fff 0x0200 0x01ff 0x0000 system area 0x4000 0x3fff instruction rom note (32 kwords) (ipr=0x0) (ipr=0x1) paging area instruction ram (31.5 kwords) boot-up rom (512 words) 0x0200 0x01ff 0x0000 0xffff 0x8000 0x7fff pd77210 pd77213 paging area (32 kwords) paging area (32 kwords) boot-up rom (512 words) note the higher 8 words of the instruction rom (0xfff8 to 0xffff) constitute system area. caution programs and data cannot be allocated to the system area, and neither can it be accessed. if these addresses are accessed, correct operation of the device is not guaranteed. a paging area in which no ipr page exists cannot be accessed. if this kind of paging area is accessed, correct operation of the device is not guaranteed.
data sheet u15203ej3v0ds 33 pd77210, 77213 7.1.2 interrupt vector table addresses 0x200 to 0x23f of the instruction memory are assigned to entry points (vectors) of interrupts. four instruction addresses are assigned to each interrupt source. four interrupt sources are assigned to each interrupt vector. there are 12 vectors. by identifying the source in the vector, the pd77210 can use 38 interrupt sources and pd77213 can use 42 interrupt sources. each of these interrupt sources can be masked by using the interrupt control register (icr0 to icr11). interrupt source vector 0123 0x200 reset reserved reserved reserved 0x204 reserved reserved reserved reserved 0x208 reserved reserved reserved reserved 0x20c reserved reserved reserved reserved 0x210 int00 int01 int02 int03 0x214 int10 int11 int12 int13 0x218 int20 int21 int22 int23 0x21c int30 int31 int32 int33 0x220 tsi input tsien pmt ch0 (tsi input) sdcr input note 0x224 tso output tsoen pmt ch1 (tso output) sdcr output note 0x228 asi input asien pmt ch2 (asi input) sddat input note (busy release) 0x22c aso output asoen pmt ch3 (aso output) sddat output note 0x230 hi input hwr pmt ch4 (hi input) reserved 0x234 ho output hrd pmt ch5 (ho output) reserved 0x238 timer ch0 timer ch1 pmt ch6 (mi input) reserved 0x23c timer ch1 timer ch0 pmt ch7 (mo output) reserved note these interrupt sources are for the pd77213 only. when using the pd77210, they are reserved. cautions 1. reset is not an interrupt but is used as an entry of a vector. 2. it is recommended that the vector of an interrupt source that is not used branch to an abnormality processing routine.
data sheet u15203ej3v0ds 34 pd77210, 77213 7.2 data memory 7.2.1 data memory map the data memory space consists of two planes: the x and y memory spaces, each of which consists of 64 kwords 16 bits. the area of 0x8000 to 0xffff is a paging area that supports a memory space of 64 kwords or more by specifying a page by using the data paging register (dpr). the dpr can be set in the same manner regardless of whether the x or y memory space is accessed. page 0x3f of dpr is a window to the external data memory. the data rom of the pd77213 exists in the paging area and is accessed as dpr = 0x0. page 0x80 of the dpr is shared by 0x0000 to 0x7fff of the internal instruction ram. the lower 16 bits of the 32-bit instruction ram constitute the x data memory, while the higher 16 bits are the y data memory. because some pins of the pd77213 are shared with the sd card interface, the area that can be accessed when the sd card interface is being used is restricted. the address pins ma13 to ma19 are shared with the sd card interface. when the sd card interface is being used, therefore, only the 13-bit address area of ma0 to ma12 (8 kwords) can be accessed. 0xffff 0x8000 0x7fff 0x3800 0x37ff 0x0000 system 0x4000 0x3fff (dpr=0x0) (dpr=0x3f) paging area 0x5000 0x4fff data ram (14 kwords) paging area note 1 (32 kwords) 0xffff 0x8000 0x7fff 0x3800 0x37ff 0x0000 0x4000 0x3fff external data memory window (32 kwords) (dpr=0x3f) peripheral (2 kwords) data ram (16 kwords) pd77210 pd77213 paging area (32 kwords) data ram (14 kwords) peripheral (2 kwords) data ram (4 kwords) data rom note 2 (32 kwords) external data memory window (32 kwords) paging area notes 1. if the paging register is set to a value other than 0x3f (external data memory window) or 0x80 (internal instruction ram area), programs and data cannot be stored to the addresses of the paging area, nor can these addresses be accessed. 2. the higher 8 words of the data rom (0xfff8 to 0xffff) constitute system area. caution programs and data cannot be allocated to the system area, and neither can it be accessed. if these addresses are accessed, correct operation of the device is not guaranteed. a paging area in which no dpr page exists cannot be accessed. if this kind of paging area is accessed, correct operation of the device is not guaranteed.
data sheet u15203ej3v0ds 35 pd77210, 77213 7.2.2 internal peripherals the internal peripherals are mapped to the internal data memory space. cautions 1. the register names shown in the above table are not reserved words in either assembler or c. to use these names in assembler or c, therefore, the user must define them. 2. the same register is accessed regardless of whether the x memory space or y memory space is accessed, provided that the address is the same. 3. different registers cannot be accessed simultaneously from the x and y memory spaces. memory-mapped peripherals (1/3) x/y memory address register name function peripheral name 0x3800 tsdt/sdt1 tdm serial data register/serial data register 1 0x3801 sst1 serial status register 1 0x3802 tsst tdm serial status register 0x3803 tfmt tdm frame format register 0x3804 ttxl tdm transfer slot register (low) 0x3805 ttxh tdm transfer slot register (high) 0x3806 trxl tdm receive slot register (low) 0x3807 trxh tdm receive slot register (high) tsio(sio1) 0x3808 to 0x380f reserved area caution do not access this area. ? 0x3810 asdt/sdt2 audio serial data register/serial data register 2 0x3811 sst2 serial status register 2 0x3812 asst audio serial status register asio(sio2) 0x3813 to 0x381f reserved area caution do not access this area. ? 0x3820 hdt host interface data register 0x3821 hst host interface status register hio 0x3822 to 0x383f reserved area caution do not access this area. ? 0x3840 mdt memory data register 0x3841 mshw memory i/f setup/hold width setting register 0x3842 mcst memory i/f control/status register 0x3843 mwait memory i/f wait register 0x3844 midx direct access index register 0x3845 madrli memory i/f input start address register (low) 0x3846 madrhi memory i/f input start address register (high) 0x3847 mofsi memory i/f input line offset register 0x3848 mleni memory i/f input line length register 0x3849 madrlo memory i/f output start address register (low) 0x384a madrho memory i/f output start address register (high) 0x384b mofso memory i/f output line offset register 0x384c mleno memory i/f output line length register mio 0x384d to 0x384f reserved area caution do not access this area. ? 0x3850 pmsa0 pmt start address register 0 pmt ch0 0x3851 pms0 pmt size register 0 0x3852 pmc0 pmt control register 0 0x3853 pmp0 pmt address pointer 0
data sheet u15203ej3v0ds 36 pd77210, 77213 memory-mapped peripherals (2/3) x/y memory address register name function peripheral name 0x3854 pmsa1 pmt start address register 1 0x3855 pms1 pmt size register 1 0x3856 pmc1 pmt control register 1 0x3857 pmp1 pmt address pointer 1 pmt ch1 0x3858 pmsa2 pmt start address register 2 0x3859 pms2 pmt size register 2 0x385a pmc2 pmt control register 2 0x385b pmp2 pmt address pointer 2 pmt ch2 0x385c pmsa3 pmt start address register 3 0x385d pms3 pmt size register 3 0x385e pmc3 pmt control register 3 0x385f pmp3 pmt address pointer 3 pmt ch3 0x3860 pmsa4 pmt start address register 4 0x3861 pms4 pmt size register 4 0x3862 pmc4 pmt control register 4 0x3863 pmp4 pmt address pointer 4 pmt ch4 0x3864 pmsa5 pmt start address register 5 0x3865 pms5 pmt size register 5 0x3866 pmc5 pmt control register 5 0x3867 pmp5 pmt address pointer 5 pmt ch5 0x3868 pmsa6 pmt start address register 6 0x3869 pms6 pmt size register 6 0x386a pmc6 pmt control register 6 0x386b pmp6 pmt address pointer 6 pmt ch6 0x386c pmsa7 pmt start address register 7 0x386d pms7 pmt size register 7 0x386e pmc7 pmt control register 7 0x386f pmp7 pmt address pointer 7 pmt ch7 0x3870 pdt0 port data register 0 0x3871 pcd0 port command register 0 0x3872 pdt1 port data register 1 0x3873 pcd1 port command register 1 0x3874 pdt2 port data register 2 pio 0x3875 pcd2 port command register 2 0x3876 pdt3 port data register 3 0x3877 pcd3 port command register 3 0x3878, 0x3879 reserved area caution do not access this area. ? 0x387a, 0x387b powc power control register peripheral stop mode
data sheet u15203ej3v0ds 37 pd77210, 77213 memory-mapped peripherals (3/3) x/y memory address register name function peripheral name 0x387c to 0x387f reserved area caution do not access this area. ? 0x3880 icr0 interrupt control register 0 0x3881 icr1 interrupt control register 1 0x3882 icr2 interrupt control register 2 0x3883 icr3 interrupt control register 3 0x3884 icr4 interrupt control register 4 0x3885 icr5 interrupt control register 5 0x3886 icr6 interrupt control register 6 0x3887 icr7 interrupt control register 7 0x3888 icr8 interrupt control register 8 0x3889 icr9 interrupt control register 9 0x388a icr10 interrupt control register 10 0x388b icr11 interrupt control register 11 intc 0x388c to 0x388f reserved area caution do not access this area. ? 0x3890 tir0 timer initial register 0 0x3891 tcr0 timer count register 0 0x3892 tcsr0 timer control/status register 0 tim0 0x3893 reserved area caution do not access this area. ? 0x3894 tir1 timer initial register 1 0x3895 tcr1 timer count register 1 0x3896 tcsr1 timer control/status register 1 tim1 0x3897 to 0x389f reserved area caution do not access this area. ? 0x38a0 cefr collect enable flag register 0x38a1 cpr0 collect page register 0 0x38a2 car0 collect address register 0 0x38a3 clir0 collect instruction data register (high) 0 0x38a4 cuir0 collect instruction data register (low) 0 0x38a5 cpr1 collect page register 1 0x38a6 car1 collect address register 1 0x38a7 clir1 collect instruction data register (high) 1 0x38a8 cuir1 collection instruction data register (low) 1 imc 0x38a9 to 0x38af reserved area caution do not access this area. ? 0x38b0 clkc clock control register clkc 0x38b1 to 0x38bf reserved area caution do not access this area. ? 0x38c0 ipr instruction paging register 0x38c1 dpr data paging register page register 0x38c2 to 0x38cf reserved area caution do not access this area. ? 0x38d0 adcr note additional i/f control register additional io 0x38d1-0x3fff reserved area caution do not access this area. ? note pd77213 only. do not access 0x38d0 of the pd77210.
data sheet u15203ej3v0ds 38 pd77210, 77213 8. general-purpose port and interrupt 8.1 general-purpose port pins the general-purpose port pins alternate with the interrupt or host interface pins. the configuration of the general-purpose port is illustrated below. port i/o interrupt controller port pin host i/o oe o i oe o i note note p0 to p7 do not alternate with the host interfave pins. 8.2 interrupt pin the general-purpose port pin functions as an interrupt pin and the signal input to the port is always input to the interrupt controller. the interrupt controller recognizes the interrupt by detecting a falling edge. the output of the general-purpose port or host interface pin can be also used as an interrupt input. pins hrd, hwr, asoen, asien, tsoen, and tsien are connected to the interrupt controller and can be used as interrupt pins.
data sheet u15203ej3v0ds 39 pd77210, 77213 9. instruction 9.1 outline of instruction one instruction consists of 32 bits. all the instructions, with some exceptions such as branch instructions, are executed with one system clock. the instruction cycle of the pd77210 is up to 6.25 ns. the instruction cycle of the pd77213 is up to 8.33 ns. the following nine types of instructions are available. (1) trinomial instructions these instructions specify an operation by the mac. as the operands, three general-purpose registers can be specified. (2) binomial instructions these instructions specify an operation by the mac, alu, or bsft. as the operands, two general-purpose registers can be specified. some of these instructions allow one immediate value to be specified instead of a general-purpose register. (3) monomial instructions these instructions specify an operation by the alu. as the operand, a general-purpose register can be specified. (4) load/store instructions these instructions specify 16-bit data transfer between memory and a general-purpose register. as the operand, any general-purpose register can be specified. (5) register-to-register transfer instructions these instructions specify transfer between a general-purpose register and another register. (6) immediate value setting instructions these instructions set an immediate value in the general-purpose registers and each register of the address operation unit. (7) branch instructions these instructions specify branching of the program. (8) hardware loop instructions these instructions specify the repetitive execution of an instruction. (9) control instructions these instructions specify program control.
data sheet u15203ej3v0ds 40 pd77210, 77213 9.2 instruction set and its operation describe an operation in the operation field of each instruction in accordance with the description method of the operation representation format of the instruction. if two or more elements are available, select one of them. (a) correspondence between representation format and selectable register the representation format and selectable register are as follows: representation format selectable register ro, ro?, ro? r0 to r7 rl, rl? r0l to r7l rh, rh? r0h to r7h re r0e to r7e reh r0eh to r7eh dp dp0 to dp7 dn dn0 to dn7 dm dmx, dmy dpx dp0 to dp3 dpy dp4 to dp7 dpx_mod dpn, dpn++, dpn ?? , dpn##, dpn%%, !dpn## (n = 0 to 3) dpy_mod dpn, dpn++, dpn ?? , dpn##, dpn%%, !dpn## (n = 4 to 7) dp_imm dpn## imm (n = 0 to 7) *xxx contents of memory at address (example) if the contents of the dp0 register are 1000, *dp0 indicates the contents of memory address 1000.
data sheet u15203ej3v0ds 41 pd77210, 77213 (b) modifying data pointer the data pointer is modified only after memory access. the result of the modification becomes valid starting from the instruction that is executed immediately after. the data pointer cannot be modified without the memory access. example operation dpn nothing is executed (value of dpn is not changed). dpn++ dpn dpn + 1 dpn ?? dpn dpn ? 1 dpn## dpn dpn + dnn (value of dn0 to dn7 corresponding to dp0 to dp7 is added.) example: dp0 dp0 + dn0 (n = 0 to 3) dpn = ((dp l + dnn) mod (dmx + 1)) + dp h dpn%% (n = 4 to 7) dpn = ((dp l + dnn) mod (dmy + 1)) + dp h !dpn## reverses bits of dpn and then accesses dpn. after memory access, dpn dpn + dnn dpn## imm dpn dpn + imm (c) instructions that can be described simultaneously those instructions that can be described simultaneously are indicated by . (d) status of overflow flag (ov) the status of the overflow flag is indicated by the following symbols: : no change : set to 1 if an overflow occurs. caution if an overflow does not occur after an operation, the overflow flag is not reset and its status remains the same as before the operation. ?
data sheet u15203ej3v0ds 42 pd77210, 77213 instruction set instructions that can be described simultaneously flag instruction group instruction name mnemonic operation trinomial binomial monomial load/store transfer immediate value branch loop control ov multiply add ro = ro + rh*rh? ro ro + rh*rh? ? multiply sub ro = ro ? rh*rh? ro ro ? rh*rh? ? signed/unsigned multiply add ro = ro + rh*rl (rl is in positive integer format.) ro ro + rh*rl ? unsigned/unsigned multiply add ro = ro + rl*rl? (rl and rl? are in positive integer format.) ro ro + rl*rl? ? 1-bit shift multiply add ro = (ro >> 1) + rh*rh? ro ro/2 + rh*rh? ? trinomial operation 16-bit shift multiply add ro = (ro >> 16) + rh*rh? ro ro/2 + rh*rh? multiply ro = rh*rh? ro rh*rh? add ro? = ro + ro? ro? ro + ro? ? immediate add ro? = ro + imm ro? ro + imm (where imm 1) ? ? ro? ro? ro ? ro? ? immediate sub ro? = ro ? imm ro? ro ? imm (where imm 1) ? ro >> rl immediate arithmetic right shift ro? = ro sra imm ro? ro >> imm logical right shift ro? = ro srl rl ro? ro >> rl immediate logical right shift ro? = ro srl imm ro? ro >> imm logical left shift ro? = ro sll rl ro? ro << rl immediate logical left shift ro? = ro sll imm ro? ro << imm and ro? = ro & ro? ro? ro & ro? immediate and ro? = ro & imm ro? ro & imm or ro? = ro | ro? ro? ro | ro? immediate or ro? = ro | imm ro? ro | imm exclusive or ro? = ro^ro? ro? ro^ro? immediate exclusive or ro? = ro^imm ro? ro^imm binomial operation less than ro? = lt (ro, ro?) if (ro < ro?) {ro? 0x0000000001} else {ro? 0x0000000000}
data sheet u15203ej3v0ds 43 pd77210, 77213 instructions that can be described simultaneously flag instruction group instruction name mnemonic operation trinomial binomial monomial load/store transfer immediate value branch loop control ov clear clr (ro) ro 0x0000000000 ? increment ro? = ro + 1 ro? ro + 1 ? ? decrement ro? = ro ? 1ro? ro ? 1 ? ? absolute value ro? = abs (ro) if (ro < 0) {ro? ? ro} else {ro? ro} ? ? 1?s complement ro? = ~ ro ro? ~ ro ? 2?s complement ro? = ? ro ro? ? ro ? ? clip ro? = clip (ro) if (ro > 0x007fffffff) {ro? 0x007fffffff} elseif (ro < 0xff80000000) {ro? 0xff80000000} else {ro? ro} ? round ro? = round (ro) if (ro > 0x007fff0000) {ro? 0x007fff0000} elseif (ro < 0xff80000000) {ro? 0xff80000000} else {ro? (ro + 0x8000) & 0xffffff0000} ? exponent ro? = exp (ro) ro? log 2 (1/ro) ? substitution ro? = ro ro? ro ? accumulated add ro? + = ro ro? ro? + ro ? ? accumulated sub ro? ? = ro ro? ro? ? ro ? ? monomial operation division ro? / = ro if (sign (ro?) = = sign (ro)) {ro? (ro? ? ro) << 1} else {ro? (ro? + ro) << 1} if (sign (ro?) = = 0) {ro? ro? + 1} ? ?
data sheet u15203ej3v0ds 44 pd77210, 77213 instructions that can be described simultaneously flag instruction group instruction name mnemonic operation trinomial binomial monomial load/store transfer immediate value branch loop control ov ro = *dpx_mod ro? = *dpy_mod ro *dpx, ro? *dpy ro = *dpx_mod *dpy_mod = rh ro *dpx, *dpy rh *dpx_mod = rh ro = *dpy_mod *dpx rh, ro *dpy parallel load/store notes 1, 2 *dpx_mod = rh *dpy_mod = rh? *dpx rh, *dpy rh? ?? dest = *dpx_mod dest? = *dpy_mod dest *dpx, dest? *dpy dest = *dpx_mod *dpy_mod = source dest *dpx, *dpy source *dpx_mod = source dest = *dpy_mod *dpx source, dest *dpy partial load/store notes 1, 2, 3 *dpx_mod = source *dpy_mod = source? *dpx source, *dpy source? dest = *addr dest *addr direct addressing load/store note 4 *addr = source *addr source dest = *dp_imm dest *dp load/store immediate index load/store note 5 *dp_imm = source *dp source dest = rl dest rl register- to-register transfer register-to-register transfer note 6 rl = source rl source rl = imm (where imm = 0 to 0xffff) rl mm dp = imm (where imm = 0 to 0xffff) dp imm dn = imm (where imm = 0 to 0xffff) dn imm immediate value setting immediate value setting dm = imm (where imm = 1 to 0xffff) dm imm notes 1. of the two mnemonics, either or both can be described. 2. after transfer, modification specified by mod is performed. 3. dest, dest? = {ro, reh, re, rh, rl}, source, source? = {re, rh, rl} 4. dest = {ro, reh, re, rh, rl}, source = {re, rh, rl}, addr = {0: x-0xffff: x (x memory), or 0: y-0xffff: y (y memory)} 5. dest = {ro, reh, re, rh, rl}, source = {re, rh, rl} 6. select any of the registers (except the general-purpose registers) as dest and source.
data sheet u15203ej3v0ds 45 pd77210, 77213 instructions that can be described simultaneously flag instruction group instruction name mnemonic operation trinomial binomial monomial load/store transfer immediate value branch loop control ov jump jmp imm pc imm register-to-register jump jmp dp pc dp subroutine call call imm sp sp + 1 stk pc + 1 pc imm register-to-register subroutine call call dp sp sp + 1 stk pc + 1 pc dp return ret pc stk sp sp ? 1 branch interrupt return reti pc stk stk sp ? 1 restores interrupt enable flag. repeat rep count start rc count rf 0 during repeat pc pc rc rc ? 1 end pc pc + 1 rf 1 loop loop count (instruction of 2 lines or more) start lc count lf 0 during loop pc pc + 1 (while pc < lea) if (pc = lea) pc lsa lc lc ? 1 end pc pc + 1 lf 1 hardware loop loop pop lpop lc lsr3 le lsr2 ls lsr1 lsp lsp ? 1 no operation nop pc pc + 1 halt halt cpu stops. stop stop cpu stops, pll, and osc can be stopped by a user condition if (ro cond) condition judgment ?? control forget interrupt fint discards interrupt request.
data sheet u15203ej3v0ds 46 pd77210, 77213 10. electrical specifications absolute maximum ratings (t a = +25 c) parameter symbol condition rating unit iv dd for dsp core ? 0.5 to + 2.0 v supply voltage ev dd for i/o pins ? 0.5 to + 4.6 v input voltage v i ? 0.5 to + 4.6 v output voltage v o v i < ev dd + 0.5 v ? 0.5 to + 4.6 v storage temperature t stg ? 65 to + 150 c operating ambient temperature t a ? 20 to + 70 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operating conditions parameter symbol condition min. typ. max. unit operating voltage iv dd for dsp core (operating speed 120 mhz max.) 1.425 1.50 1.65 v for dsp core (operating speed 160 mhz max.) note 1.55 1.60 1.65 v ev dd for i/o pins 2.7 3.3 3.6 v input voltage v i 0ev dd v note pd77210 only capacitance (t a = +25 c, iv dd = 0 v, ev dd = 0 v) parameter symbol condition min. typ. max. unit input capacitance c i 10 pf output capacitance c o 10 pf i/o capacitance c io f = 1 mhz, pins other than those tested: 0 v 10 pf
data sheet u15203ej3v0ds 47 pd77210, 77213 dc characteristics (unless otherwise specified, t a = ? ? ? ? 20 to + 70 c, with iv dd and ev dd within recommended operating condition range) parameter symbol condition min. typ. max. unit high level input voltage v ihn pins other than below 0.7 ev dd ev dd v v ihc clkin 0.7 ev dd ev dd v v ihs reset, p0 to p15, tsck, tsien,tsoen, asck, asien, asoen 0.8 ev dd ev dd v low level input voltage v iln pins other than below 0 0.2 ev dd v v ilc clkin 0 0.2 ev dd v v ils reset, p0 to p15, tsck, tsien,tsoen, asck, asien, asoen 0 0.2 ev dd v high level output voltage v oh i oh = ? 100 a 0.8 ev dd v low level output voltage v ol i ol = 2.0 ma 0.2 ev dd v high level input leakage current i lhn v i = ev dd 010 a low level input leakage current i lln v i = 0 v ? 10 0 a high impedance leakage current i lz 0 v v i ev dd 0 ? 10 a pull-up pin current i pui tdi, tms, 0 v v i ev dd 20 70 200 a pull-down pin current i pdi trst, 0 v v i ev dd ? 20 ? 70 ? 200 a i dd during operating, fclk = 100 mhz, pll multiple rate x10 35 note 1 70 note 2 ma i ddh in halt mode, fclk = 100 mhz, pll multiple rate x 10, division rate 1/1 20 note 3 ma internal supply current [fclkin = 10 mhz, iv dd = 1.5 v, v ihn = v ihc = v ihs = ev dd , v il = 0 v, no load, t a = 25 c] i dds in stop mode note 4 , pd77210 240 a fclk = 0 hz, pll stop pd77213 120 notes 1. the value is when mac with dual load instruction 50% + nop instruction 50% are executed. it is roughly estimated at 0.35 ma/mhz. 2. the value is when a special program that brings about frequent switching inside the device is executed. it is roughly estimated at 0.7 ma/mhz. 3. the value is when the division rate is 1/1. it is roughly estimated at 0.2 ma/mhz + i dds using the divided clock. 4. the value in stop mode is the value when pll is stopped.
data sheet u15203ej3v0ds 48 pd77210, 77213 common test criteria of switching characteristics 0.8 ev dd 0.5 ev dd 0.2 ev dd 0.8 ev dd 0.5 ev dd 0.2 ev dd test points reset, p0 to p15, tsck, tsien, tsoen, asck, asien, asoen 0.7 ev dd 0.5 ev dd 0.2 ev dd 0.7 ev dd 0.5 ev dd 0.2 ev dd test points input (other than above) 0.5 ev dd 0.5 ev dd test points output
data sheet u15203ej3v0ds 49 pd77210, 77213 ac characteristics (t a = ? ? ? ? 20 to + 70 c, with iv dd and ev dd within recommended operating condition range) clock timing requirements parameter symbol condition min. typ. max. unit clkin cycle time note 1 t ccx 62.5 ns clkin high level width t wcxh 12.5 ns clkin low level width t wcxl 12.5 ns clkin rise/fall time t rfcx 5ns internal clock cycle time t cc over 120 mhz( pd77210 only) 6.25 ns requirements under 120 mhz 8.33 ns pll lock-up time t lpll 300 s pll lock frequency note 1 t cpll when boot:p3 = 0 note 2 120 160 mhz when boot:p3 = 1 80 120 mhz notes 1. the clkin cycle time must accord with the pll lock frequency. it is therefore necessary to satisfy both the clkin cycle time condition of 62.5 ns (min.) and the pll lock frequency condition of a multiplied frequency in the range of 80 to 160 mhz. 2. in the pd77213, it can be set only when an external memory boot is being used. switching characteristics parameter symbol condition min. typ. max. unit internal clock cycle note t cc t ccx m nns clkout cycle time t cco t cc ns clkout width t wco n = 1 t cc 2ns n 2 high level width t cc nns low level width t cc ? t cc n ns clkout rise/fall time t rfco 5ns clkout delay time t dco 6.25 ns note m: multiple ratio, n: division ratio (pll, divider)
data sheet u15203ej3v0ds 50 pd77210, 77213 clock i/o timing internal clock clkin clkout t ccx t cc, t cpll t wcxh t wcxl t rfcx t rfcx t cco t dco t wco t wco t rfco t rfco
data sheet u15203ej3v0ds 51 pd77210, 77213 reset, interrupt, system control, timer timing requirements parameter symbol condition min. typ. max. unit reset low level width t w(rl) 6 t ccx note 1 ns cstop high level width t w(cstoph) 12 t cc note 2 ns cstop recovery time t rec(cstop) 12 t cc note 2 ns intmn low level width t w (intl) 6 t cc note 3 ns intmn recovery time t rec (int) 6 t cc note 3 ns notes 1. when reset timing, it is specified by input clock. 2. when stop or halt mode, it is specified by divided clock. 3. interrupt can input by tsien, tsoen, asien, and asoen pins other than interrupt pins. the interrupt pins function alternately as pins p0 to p15. remark intmn m, n = 0 to 3 switching characteristics parameter symbol condition min. typ. max. unit stops output delay time t dstp 06.25ns halts output delay time t dhlt 06.25ns timout output delay time t dtim 06.25ns timout output width t wtim 4 t cc ns reset timing reset t w(rl) wakeup timing cstop t w(cstoph) t rec(cstop) interrupt timing intmn t w(intl) t rec(int)
data sheet u15203ej3v0ds 52 pd77210, 77213 standby mode status output timing internal clock stops t dstp halts t dhlt t dhlt internal status cstop fetch next instruction of stop or halt execution stop or halt instruction remarks 1. internal clock cycle is changed or stopped to be fixed to low level when stop or halt mode. 2. stops pin is become low level asynchronously by cstop pin rising edge. timer time out status output timing internal clock timout detect time out t dtim t dtim internal status t wtim
data sheet u15203ej3v0ds 53 pd77210, 77213 external data memory access timing requirements parameter symbol condition min. typ. max. unit md setup time t sumdi 17.5 ns md hold time t hmdi 0ns mholdrq setup time t suhrq 11.25 ns mholdrq hold time t hhrq 0ns mwait setup time t suwait 11.25 ns mwait hold time t hwait 0ns switching characteristics parameter symbol condition min. typ. max. unit ma output delay time t dma 06.25ns mrd output delay time t dmrd 06.25ns mwr output delay time t dmwr 06.25ns md output delay time t dmdo 06.25ns mbstb output delay time t dbs 06.25ns mholdak output delay time t dhak 06.25ns
data sheet u15203ej3v0ds 54 pd77210, 77213 external data memory access timing (read) t sumdi t dmrd t hwait internal colck ma0 to ma19 md0 to md15 mrd mwait t dma t dmrd t suwait t suwait t hwait t hmdi t dma mbstb t dbs t dbs remark in the pd77213, it is possible to shift fall timing of mrd pin by cycle unit, by setting of mshw register. external data memory access timing (write) t hwait internal clock ma0 to ma19 md0 to md15 mwr mwait t dma t suwait t suwait t hwait t dmdo t dmwr hi-z hi-z t dmdo t dmdo t dma mbstb t dbs t dbs t dmwr remark it is possible to shift rise/fall timing of mwr pin by cycle unit, by setting of mshw register.
data sheet u15203ej3v0ds 55 pd77210, 77213 bus arbitration timing internal colck t suhrq mholdrq mholdak ma0 to ma19, md0 to md15, mrd, mwr (bus busy) bus busy t dhak t suhrq bus idle bus idle (bus busy) t hhrq t dhak bus release t hhrq t dma ,t dmdo ,t dmrd ,t dmwr hi-z t dma ,t dmdo ,t dmrd ,t dmwr
data sheet u15203ej3v0ds 56 pd77210, 77213 general-purpose i/o port timing requirements parameter symbol condition min. typ. max. unit port input setup time t supi 11.25 ns port input hold time t hpi 6.25 ns switching characteristics parameter symbol condition min. typ. max. unit port output delay time t dpo 06.25ns general-purpose i/o port timing internal clock p0 to p15 (output) t dpo t hpi t supi p0 to p15 (input)
data sheet u15203ej3v0ds 57 pd77210, 77213 host interface timing requirements parameter symbol condition min. typ. max. unit hrd low level width, recovery time t whrd 3 t cc ns hwr low level width, recovery time t whwr 3 t cc ns hd setup time t suhdi 6.25 ns hd hold time t hhdi 6.25 ns ha, hcs setup time t suha 3ns ha,hcs hold time t hha 0ns switching characteristics parameter symbol condition min. typ. max. unit hre output delay time t dre 0 11.25 ns hwe output delay time t dwe 0 11.25 ns hd output delay time t dhd 0 11.25 ns
data sheet u15203ej3v0ds 58 pd77210, 77213 host read interface timing interanal clock hrd t dre t dhd t hha t whrd t dhd t whrd t suha t dre hcs, ha0, ha1 hd0 to hd15 hre hi-z hi-z host write interface timing internal clock hwr t dwe t hhdi t hha t whwr t whwr t suha t dwe hcs, ha0, ha1 hd0 to hd15 hwe t suhdi
data sheet u15203ej3v0ds 59 pd77210, 77213 serial interface (standard serial mode/ tdm serial mode) timing requirements parameter symbol condition min. typ. max. unit asck cycle time t csc 50 and 2 t cc ns asck high /low level width t wsc 25 ns asck rise/fall time t rfsc 20 ns serial input setup time t suser 12.5 ns serial input hold time t hser 12.5 ns switching characteristics parameter symbol condition min. typ. max. unit serial output delay time t dser 0 17.5 ns
data sheet u15203ej3v0ds 60 pd77210, 77213 serial output timing 1 asck, tsck t rfsc tsorq asoen, tsoen aso, tso 1st last t hser t dser t dser t hser t suser t suser t hser t dser t wsc t wsc t csc t dser t rfsc hi-z note when tdm mode, tso output value is delay for a bit according to tdm setting value. serial output timing 2 (during successive output) asck, tsck t rfsc tsorq asoen, tsoen aso, tso 1st last t dser t hser t suser t dser t wsc t wsc t csc t dser t rfsc last t hser hi-z note when tdm mode, tso output value is delay for a bit or dummy cycle (high impedance) is inserted, according to tdm setting value.
data sheet u15203ej3v0ds 61 pd77210, 77213 serial input timing 1 asck, tsck tsiak asien, tsien asi, tsi t csc t wsc t wsc t dser t suser t hser t suser t hser t dser t suser t hser 1st 2nd t rfsc t rfsc 3rd note when tdm mode, tsi input value is delay for a bit according to tdm setting value. serial input timing 2 (during successive input) asck, tsck tsiak asien, tsien asi, tsi t csc t wsc t wsc t dser t suser t hser t dser t suser t hser 1st 3rd t rfsc t rfsc last last?1 2nd note when tdm mode, tsi input value is delay for a bit or skip cycle is input, according to tdm setting value.
data sheet u15203ej3v0ds 62 pd77210, 77213 serial interface (audio serial mode) timing requirements parameter symbol condition min. typ. max. unit mclk cycle time t cmc master mode 50 and 2 t cc ns mclk high/low level width t wmc master mode 25 ns mclk rise/fall time t rfmc master mode 20 ns bclk cycle time t cbc slave mode 50 and 8 t cc ns bclk high/low level width t wbc slave mode 25 ns bclk rise/fall time t rfbc slave mode 20 ns serial input setup time t suaser slave mode 12.5 ns master mode 25.0 ns serial input hold time t haser slave mode 12.5 ns master mode 25.0 ns switching characteristics parameter symbol condition min. typ. max. unit bclk cycle time t cbc master mode 50 and 8 t cc ns bclk high/low level width t wbc master mode 25 ns bclk rise/fall time t rfbc master mode 5 ns serial output delay time t daser master mode ? 12.5 + 25.0 ns slave mode 0 17.5 ns
data sheet u15203ej3v0ds 63 pd77210, 77213 audio serial clock timing mclk t cmc t wmc t wmc t rfmc t rfmc audio serial master mode timing bclk (output) t rfbc lrclk (output) t daser t wbc t wbc t cbc t daser t rfbc aso t daser asi t haser t suaser audio serial slave mode timing bclk (input) t rfbc lrclk (input) t suaser t wbc t wbc t cbc t rfbc aso t daser asi t haser t suaser t suaser
data sheet u15203ej3v0ds 64 pd77210, 77213 caution if noise is superimposed on the serial clock, the serial interface may be deadlocked. bear in mind the following points when designing your system: ? reinforce the wiring for power supply and ground (if noise is superimposed on the power and ground lines, it has the same effect as if noise were superimposed on the serial clock). shorten the wiring between the device's asck, tsck, bclk pins, and clock supply source. do not cross the signal lines of the serial clock with any other signal lines. do not route the serial clock line in the vicinity of a line through which a high alternating current flows. supply the clock to the asck, tsck, bclk pins of the device from the clock source on a one- to-one basis. do not supply clock to several devices from one clock source. exercise care that the serial clock does not overshoot or undershoot. in particular, make sure that the rising and falling of the serial clock waveform are clear. make sure that the serial clock rises and falls linearly. the serial clock must not bound. noise must not be superimposed on the serial clock. the serial clock must not rise or fall step-wise.
data sheet u15203ej3v0ds 65 pd77210, 77213 sd card interface ( pd77213 only) timing requirements parameter symbol condition min. typ. max. unit sdcr input setup time t susdcr input response 10 ns sdcr input hold time t hsdcr input response 0 ns sddat input setup time t susdd input data 10 ns sddat input hold time t hsdd input data 0 ns switching characteristics parameter symbol condition min. typ. max. unit sdclk cycle time t csdc n x t cc note ns sdclk high level width t wsdc(h) 2 t cc ns sdclk low level width t wsdc(l) t csdc ? t wsdc(h) ns sdclk rise/fall time t rfsdc 5ns sdcr output delay time t dsdcr output command 10 ns sdcr output valid time t vsdcr output command 0 ns sddat output delay time t dsdd output data 10 ns sddat output valid time t vsdd output data 0 ns note n : sd card clock division ratio
data sheet u15203ej3v0ds 66 pd77210, 77213 sdcr timing sdclk sdcr (output) t dsdcr t hsdcr t susdcr sdcr (input) t vsdcr t csdc t wsdc(l) t wsdc(h) t rfsdc t rfsdc sddat timing sdclk sddat0 (output) t dsdd t hsdd t susdd sddat0 (input) t vsdd t csdc t wsdc(l) t wsdc(h) t rfsdc t rfsdc remark the sdmon pin functions alternately as the external data memory interface pin ma13. when accessing a peripheral register related to the sd card interface, the sdmon (ma13) pin becomes high level, and the ma0 to ma12 pins become low level. for the timing of these pins, refer to external data memory access .
data sheet u15203ej3v0ds 67 pd77210, 77213 debugging interface (jtag) timing requirements parameter symbol condition min. typ. max. unit tck cycle time t ctck 50 and 2 t cc note ns tck high/low level width t wtck 25 ns tck rise/fall time t rftck 20 ns tdi input setup time t sutdi 12.5 ns tdi input hold time t htdi 12.5 ns input pin setup time t sujin 12.5 ns input pin hold time t hjin 12.5 ns trst low level width t wtrst 100 ns note when using debugger, the value is 50 and 2 t ccx (min.). switching characteristics parameter symbol condition min. typ. max. unit tdo output delay time t dtdo 0 17.5 ns output pin output delay time t djout 17.5 ns
data sheet u15203ej3v0ds 68 pd77210, 77213 debugging interface timing t ctck t wtck t wtrst t sutdi t htdi t dtdo t sujin t hjin valid valid t djout t wtck t rftck t rftck valid valid tck trst tms, tdi tdo capture state update state remark for details of jtag, refer to ieee1149.1 .
data sheet u15203ej3v0ds 69 pd77210, 77213 11. package drawings 144-pin plastic lqfp (fine pitch) (20x20) item millimeters note a 22.0 0.2 b 20.0 0.2 c 20.0 0.2 d f 1.25 22.0 0.2 s144gj-50-8en-1 s 1.6 max. k 1.0 0.2 l 0.5 0.2 r g 1.25 h 0.22 0.05 i 0.08 j 0.5 (t.p.) m 0.17 n 0.08 p 1.4 0.05 q 0.10 0.05 + 0.03 ? 0.07 each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. s s m 108 73 136 109 144 72 37 detail of lead end i j f g h q r p k m l n cd s a b 3 + 4 ? 3
data sheet u15203ej3v0ds 70 pd77210, 77213 161-pin plastic fbga (10x10) item millimeters d 10.00 0.10 e 10.00 0.10 ze zd p161f1-65-da2 y1 0.20 zd 0.775 ze 0.775 w 0.20 a 1.23 0.10 a1 0.30 0.05 a2 0.93 b 0.40 0.05 x 0.08 y 0.10 a index mark a2 a1 e 0.65 ? e s w b s wa a b s y s y1 s s x bab m 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p e d
data sheet u15203ej3v0ds 71 pd77210, 77213 12. recommended soldering conditions the pd77210 family should be soldered and mounted under the following recommended conditions. for the details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact your nec sales representative. surface mounting type soldering conditions pd77210f1-da2 : : : : 161-pin plastic fine pitch bga (10 x 10) pd77213f1-xxx-da2 : : : : 161-pin plastic fine pitch bga (10 x 10) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature : 235 c, time : 30 sec. max. (at 210 c or higher). count : two times or less exposure limit : 7 days note (after that prebaking is necessary at 125 c for 10 to 72 hours) ir35-107-2 pd77210gj-8en : : : : 144-pin plastic lqfp (fine pitch) (20 x 20) pd77213gj-xxx-8en : : : : 144-pin plastic lqfp (fine pitch) (20 x 20) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature : 235 c, time : 30 sec. max. (at 210 c or higher). count : two times or less exposure limit : 3 days note (after that prebaking is necessary at 125 c for 10 to 72 hours) ir35-103-2 partial heating pin temperature : 300 c max. , time : 3 sec. max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65 % rh or less for the allowable storage period. caution do not use different soldering methods together (except for the partial heating).
data sheet u15203ej3v0ds 72 pd77210, 77213 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-3067-5800 fax: 01-3067-5899 nec electronics (france) s.a. madrid office madrid, spain tel: 091-504-2787 fax: 091-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. novena square, singapore tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp, brasil tel: 11-6462-6810 fax: 11-6462-6829 j01.2
data sheet u15203ej3v0ds 73 pd77210, 77213 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd77210,77213 the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. license not needed : pd77210f1-da2, pd77210gj-8en the customer must judge the pd77213f1-xxx-da2, pd77213gj-xxx-8en m8e 00. 4 the information in this document is current as of november, 2001. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual pr operty rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual pr operty rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": tr ansportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if cust omers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

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